- 01US patent allows graphene on non-metallic surfaces.
- 02Low-temp process (<400°C) bonds graphene to dielectrics.
- 03Graphene as diffusion barrier in interconnects.
Adisyn (ASX: AI1) has secured allowance from the US Patent and Trademark Office for a third patent that extends its graphene deposition protection to non-metallic surfaces.
The patent covers a method for depositing graphene directly onto non-metallic materials such as dielectrics, complementing Adisyn’s earlier allowed patents covering graphene deposition on metallic surfaces and resulting metal-based interconnect products.
Its claims include a low-temperature process that keeps the underlying surface below 400°C, allowing graphene to be deposited and chemically bonded without damaging the material beneath it.
Adisyn says the new protection gives it intellectual property coverage across both sides of the barrier interface used in semiconductor interconnect structures.
Barrier Interface Protection
Traditional semiconductor interconnects combine copper wiring with a barrier layer and a surrounding dielectric layer, with the barrier intended to prevent copper atoms migrating into the insulating material.
The newly allowed claims cover structures in which graphene acts as that diffusion barrier between the conducting wire and surrounding dielectric, including along the sidewalls of the interconnect.
Because the dielectric itself is primarily non-metallic, the patent adds protection for graphene deposited directly on that surface rather than only on the metal side of the interface.
“This patent happens to be built on one of our earliest priority filings, which speaks to the depth of thinking that has gone into this platform from the outset,” executive chair Kevin Crofton said.
Low-Temperature Process
The allowed method uses a graphene molecular precursor capable of forming a covalent bond directly with the non-metallic surface, enabling the graphene layer to be formed without damaging the underlying material.
Maintaining the process below 400°C is consistent with Adisyn’s broader approach to low-temperature graphene deposition for semiconductor manufacturing environments.
The patent also covers in-process quality verification using at least one of Raman scattering, contact angle measurement, or fluorescence detection to confirm or monitor the deposited graphene layer.
Adisyn considers those verification methods a potential pathway towards real-time process control during manufacture as it develops its graphene deposition platform.
Scaling Case For Graphene
Adisyn is targeting semiconductor architectures below five nanometres (nm), where shrinking wire spacing increases the proportion of available space taken by barrier and dielectric layers.
The company refers to this constraint as the “barrier tax”, because those protective layers cannot be scaled down indefinitely without compromising their role in electrical containment and insulation.
Adisyn has previously demonstrated graphene deposition at approximately 1nm thickness, which it says could allow more of the available chip area to be devoted to transistor density if graphene replaces thicker conventional barriers.
“Combined with our other two allowed US patents, we now have a strong complementary intellectual property position as we continue to advance commercialisation of this breakthrough technology," Mr Crofton added.
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